In the last lesson we simulated more complicated digital circuits with Prolog.
Here's one more. Notice how the intermediate outputs can be labeled and mapped as inputs into downstream units. Prolog is happy to unify them all and simulate the circuit for us.
Now you try. __none
Type your code here:
See your results here:
We can also insist on some inputs or outputs, allowing Prolog to tell us what combination will make it all work. Try this goal, that insists on having input A=1 and the output of 0: goal: circuit1(1,B,C,D,0).
*This circuit was adapted from "Clause and Effect," by. W. Clocksin, Ch. 7.
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